Open borders for system-on-a-chip buses: A wire format for connecting large physics controls
Kreider, M, Baer, R, Beck, D, Tepestra, W, Davies, John N, Grout, Vic, Lewis, J, Serrano, J and Wlostowski, T (2012) Open borders for system-on-a-chip buses: A wire format for connecting large physics controls. American Physical Review, Special Topics – Accelerators and Beams, 15 (8). pp. 1-10. ISSN 1098-4402
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Abstract
System-on-a-chip (SoC) bus systems are typically confined on-chip and rely on higher level components to communicate with the outside world. The idea behind the EtherBone (EB) protocol is to extend the reach of the SoC bus to remote field-programmable gate arrays or processors. The EtherBone core implementation connects a Wishbone (WB) Ver. 4 Bus via a Gigabit Ethernet based network link to remote peripheral devices. EB acts as a transparent interconnect module towards attached WB Bus devices. EB was developed in the scope of the WhiteRabbit Timing Project at CERN and GSI/FAIR. WhiteRabbit will make use of EB as a means to issue commands to its timing nodes and control connected accelerator hardware.
| Item Type: | Article |
|---|---|
| Keywords: | EtherBone, WhiteRabbit, GSI/FAIR, Accelerator Timing Project, System-on-a-chip (SoC) bus systems |
| Divisions: | ?? GlyndwrUniversity ?? |
| Depositing User: | Mr Stewart Milne |
| Date Deposited: | 06 Aug 2015 13:14 |
| Last Modified: | 11 Dec 2017 20:08 |
| URI: | https://glyndwr.repository.guildhe.ac.uk/id/eprint/8324 |
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