Algorithmic analysis and hardware implementation of a two-wire-interface communication analyser

Sharp, Andrew and Schinagl, Peter (2017) Algorithmic analysis and hardware implementation of a two-wire-interface communication analyser. In: 7th IEEE Int. Conference on Internet Technologies and Applications ITA-17, 12-15 September 2017, Glyndwr University, Wrexham.

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Abstract

This paper discusses the development of an algorithm for the data analysis to monitor Two-Wire-Interface operation in order to improve the reliability of communication. This algorithm is designed to improve code-efficiency with regards to hardware modelling. An algorithm for the protocol used in the Standard-Mode, Fast-Mode, Fast-Mode Plus and High-Speed-Mode was developed. The proposed algorithm has been derived using the bus protocol specification and implemented in hardware via a hardware description language. The correct operation of the algorithm was proofed by applying the hardware system on a sample communication. The paper also describes the development process of embedded systems and provides information on aspects regarding hardware modelling including a mathematical description of the TWI protocol is provided.

Item Type: Conference or Workshop Item (Paper)
Divisions: Applied Science, Computing and Engineering
Depositing User: Hayley Dennis
Date Deposited: 16 Apr 2018 11:11
Last Modified: 16 Apr 2018 11:11
URI: http://glyndwr.repository.guildhe.ac.uk/id/eprint/17289

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